During the manufacture of integrated circuits on semiconductor wafers, chemical mechanical polishing (CMP) processes are often used to planarize layers of deposited material. For instance, when trenches and vias are etched into a dielectric layer and filled with copper metal during a dual damascene process, a CMP process may follow to polish away any excess copper that has deposited onto the surface of the dielectric layer.
Typical CMP processes suffer from various drawbacks. The CMP process can cause dishing and erosion of the metal layer. Some areas of the metal layer may become over-polished while other areas become under-polished, causing the surface topography of the metal layer to be highly uneven. This uneven topography may accumulate as additional metal layers are deposited may lead to variations of final metal dimensions and electrical performance across the integrated circuit.
Since the polishing is uneven over the surface of the wafer, conventional CMP methods require that the wafer be intentionally over-polished to ensure that all of the metal is removed from the surface of the dielectric layer. Unfortunately, over-polishing results in the loss of metal within the features and the loss of a portion of the dielectric layer, yielding trenches and vias with lower metal volume and decreased aspect ratios.
Other drawbacks include reduced selectivity between the metal and the dielectric material due to the mechanical component of the CMP process, difficulty in ascertaining when a predetermined thickness has been reached when polishing down a layer, contamination due to wetting issues, accidental overexposing layers of material, and the force of the CMP process causing scratches or damage to the surface of a semiconductor wafer. Accordingly, improved processes are needed for the removal of excess metal from the surface of a semiconductor wafer.